Jeremiah Leary
@jeremiah-c-learyI am an HDL (VHDL and Verilog) developer interested in learning software so I can create HDL specific tools to ease the burden of developing HDL.
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I-Shaped Developer
I-shapedSpecialist — deep expertise in Python
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13
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0
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+18%
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Style guide enforcement for VHDL
HDL IP manager with similar capabilities as software package managers.
Documentation on how to perform static timing, with detailed examples on writing constraints and how to validate timing reports.
Suppresses warnings in EDA logfiles.
A tool to validate timing constraints are correct.
a small dungeon crawl game, very basic
A tool for estimatating work using relative estimates.
My Resume...on Git Hub...woot!!
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